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field- and factory-programmable spread spectrum clock generator for emi reduction cy25100 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07499 rev. *c revised february 8, 2004 features ? wide operating output (ssclk) frequency range ? 3?200 mhz ? programmable spread spectr um with nominal 31.5-khz modulation frequency ? center spread: 0 .25% to 2.5% ? down spread: ?0.5% to ?5.0% ? input frequency range ? external crystal: 8?30 mhz fundamental crystals ? external reference: 8?166 mhz clock ? integrated phase-locked loop (pll) ? field-programmable ? cy25100scf and cy25100sif, 8-pin soic ? cy25100zcf and cy25100zif, 8-pin tssop ? programmable crystal load capacitor tuning array ? low cycle-to-cycle jitter ? 3.3v operation ? commercial and industrial operation ? spread spectrum on/off function ? power-down or output enable function benefits ? services most pc peripheral s, networking, and consumer applications. ? provides wide range of spread percentages for maximum electromagnetic interference (e mi) reduction, to meet reg- ulatory agency electromagnetic compliance (emc) require- ments. reduces development and manufacturing costs and time-to-market. ? eliminates the need for expensive and difficult to use high- er-order crystals. ? internal pll to generate up to 200-mhz output. able to gen- erate custom frequencies from an external crystal or a driv- en source. ? in-house programming of samples and prototype quantities is available using the cy3672 programming kit and cy3690 (tssop) or cy3691 (soic) socket adapter. pro- duction quantities are available through cypress?s val- ue-added distribution partners or by using third-party pro- grammers from bp microsystems, hilo systems, and others. ? enables fine-tuning of output clock frequency by adjusting c load of the crystal. eliminates the need for external c load capacitors. ? suitable for most pc, consumer, and networking applica- tions ? application compatibility in standard and low-power sys- tems ? provides ability to enable or disable spread spectrum with an external pin. ? enables low-power state or output clocks to high-z state. logic block diagram pll with modulation control programmable configuration output dividers and mux 3 2 4 8 1 5 7 6 vdd vss refclk ssclk xout xin pd# or oe sson# rfb c xout c xin 4 8 vdd 6 7 vss refclk sson# 1 2 3 xout xin/clkin pd#/oe ssclk 5 pin configuration cy25100 8-pin soic/tssop
cy25100 document #: 38-07499 rev. *c page 2 of 11 general description the cy25100 is a spread spectrum clock generator (sscg) ic used for the purpose of reducing emi found in today?s high-speed digital electronic systems. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the input clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies are greatly reduced. this reduction in radiated energy can significantly reduc e the cost of complying with regulatory agency (emc) requirements and improve time-to-market without degr ading system performance. the cy25100 uses a factory/ field-programmable configu- ration memory array to synthesize output frequency, spread%, crystal load capacitor, reference clock output on/off, spread spectrum on/off function and pd#/oe options. the spread% is programmed to either center spread or down spread with various spread percentages. the range for center spread is from 0.25% to 2.50%. the range for down spread is from ?0.5% to ?5.0%. contact the factory for smaller or larger spread % amounts if required. the input to the cy25100 can be either a crystal or a clock signal. the input frequency range for crystals is 8?30 mhz, and for clock signals is 8?166 mhz. the cy25100 has two clock outputs, refclk and ssclk. the non-spread spectrum refc lk output has the same frequency as the input of the cy25100. the frequency modulated ssclk output can be programmed from 3?200 mhz. the cy25100 products are available in an 8-pin soic and tssop packages with commercial and industrial operating temperature ranges. pin description pin name description 1vdd 3.3v power supply . 2xout crystal output . leave this pin floating if external clock is used. 3 xin/clkin crystal input or reference clock input . 4 pd#/oe power-down pin : active low . if pd# = 0, the pll and xtal are powered down, and outputs are weakly pulled low. output enable pin : active high . if oe = 1, ssclk and refclk are enabled. user has the option of choosi ng either pd# or oe function. 5 vss power supply ground . 6refclk buffered reference output . 7 ssclk spread spectrum clock output . 8 sson# spread spectrum control . 0 = spread on. 1 = spread off. table 1. pin function input frequency total xtal load capacitance output frequency spread percent (0.5% ? 5%, 0.25% intervals) reference output power-down or output enable frequency modulation pin name xin and xout xin and xout ssclk ssclk refout pd#/oe ssclk pin# 3 and 2 3 and 2 7 7 6 4 7 unit mhz pf mhz % on or off select pd# or oe khz program value enter data enter data enter data enter data enter data enter data 31.5
cy25100 document #: 38-07499 rev. *c page 3 of 11 programming description field-programmable cy25100 the cy25100 is programmed at t he package level, i.e., in a programmer socket. the cy25100 is flash-technology based, so the parts can be reprogrammed up to 100 times. this allows for fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. samples and small prototype quantities can be programmed on the cy3672 programmer with cy3690 (tssop) or cy3691 (soic) socket adapter. cyberclocks ? online software cyberclocks ? online software is a web-based software appli- cation that allows the user to custom-configure the cy25100. all the parameters in table 1 given as ?enter data? can be programmed into the cy25100 . cyberclocks on line outputs an industry-standard jedec file used for programming the cy25100. for information regarding spread spectrum software programming solutions, please contact your local cypress sales or field application engineer (fae), representative for details. cy3672 ftg programming kit and cy3690/cy3691 socket adapter the cypress cy3672 ftg programmer and cy3690/cy3691 socket adapter are needed to program the cy25100. the cy3690 enables user to program cy25100zcf and cy25100zif (tssop) and cy3691 gives the user the ability to program cy25100scf and cy25100sif (soic). each socket adapter comes with sm all prototype quantities of cy25100. the cy3690/cy3691 is a separate orderable item, so the existing users of t he cy3672 ftg development kit or cy3672-prg programmer need to order only the socket adapters to program the cy25100. factory-programmable cy25100 factory programming is available for volume manufacturing by cypress. all requests must be submitted to the local cypress field application engineer (fae) or sales representative. a sample request form (refer to ?cy25100 sample request form? at www.cypress.com) must be completed. once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. this part number will be used for additional sample requests and production orders. additional information on the cy25100 can be obtained from the cypress web site at www.cypress.com. product functions input frequency (xin, pin 3 and xout , pin 2) the input to the cy25100 can be a crystal or a clock. the input frequency range for crystals is 8 to 30 mhz, and for clock signals is 8 to 166 mhz. c xin and c xout (pin 3 and pin 2) the load capacitors at pin 1 ( c xin ) and pin 8 ( c xout ) can be programmed from 12 pf to 60 pf with 0.5-pf increments. the programmed value of these on-chip crystal load capacitors are the same (xin = xout = 12 to 60 pf). the required values of c xin and c xout can be calculated using the following formula: c xin = c xout = 2c l ? c p where c l is the crystal load capacitor as specified by the crystal manufacturer and c p is the parasitic pcb capacitance. for example, if a fundamental 16-mhz crystal with c l of 16-pf is used and c p is 2 pf, c xin and c xout can be calculated as: c xin = c xout = (2 x 16) ? 2 = 30 pf. if using a driven reference, set c xin and c xout to the minimum value 12 pf. output frequency, ssclk output (ssclk, pin 7) the modulated frequency at the ssclk output is produced by synthesizing the input reference clock. the modulation can be stopped by sson# digital cont rol input (sson# = high, no modulation). if modulation is stopped, the clock frequency is the nominal value of the synthesized frequency without modulation (spread % = 0). the range of synthesized clock is from 3?200 mhz. spread percentage (ssclk, pin 7) the ssclk spread can be pr ogrammed at any percentage value from 0.25% to 2.5% for center spread and from ?0.5% to ?5.0% down spread. reference output (refout, pin 6) the reference clock output has the same frequency and the same phase as the input clock. this output can be programmed to be enabled (clock on) or disabled (high-z, clock off). if this output is not needed, it is recommended that users request the disabled (high-z, clock off) option. frequency modulation the frequency modulation is programmed at 31.5 khz for all ssclk frequencies from 3 to 200 mhz. contact the factory if a higher-modulation frequency is required. power-down or output enable (pd# or oe, pin 4): the part can be programmed to include either pd# or oe function. pd# function powers down the oscillator and pll. the oe function disables the outputs.
cy25100 document #: 38-07499 rev. *c page 4 of 11 absolute maximum rating supply voltage (v dd ) ........................................?0.5 to +7.0v dc input voltage...................................... ?0.5v to v dd + 0.5 storage temperature (non-condensing)..... ?55 c to +125 c junction temperature ................................ ?40 c to +125 c data retention @ tj = 125 c............................... > 10 years package power dissipation...................................... 350 mw static discharge voltage.......................................... > 2000v (per mil-std-883, method 3015) recommended crystal specifications parameter description comments min. typ. max. unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 8 ? 30 mhz c lnom nominal load capacitance internal load caps 6 ? 30 pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3??? dl crystal drive level no external series resistor assumed ? 0.5 2 mw operating conditions parameter description min. typ. max. unit v dd supply voltage 3.13 3.30 3.45 v t a ambient commercial temperature 0 ? 70 c ambient industrial temperature ?40 ? 85 c c load max. load capacitance @ pin 6 and pin 7 ? ? 15 pf f ref external reference crystal (fundamental tuned crystals only) 8?30mhz external reference clock 8 ? 166 mhz f ssclk ssclk output frequency, c load = 15 pf 3 ? 200 mhz f refclk refclk output frequency, c load = 15 pf 8 ? 166 mhz f mod spread spectrum modulati on frequency 30.0 31.5 33.0 khz t pu power-up time for all vdds to reach minimum spec- ified voltage (power ramp must be monotonic) 0.05 ? 500 ms dc electrical characteristics parameter description condition min. typ. max. unit i oh output high current v oh = v dd ? 0.5, v dd = 3.3v (source) 10 12 ma i ol output low current v ol = 0.5, v dd = 3.3v (sink) 10 12 ma v ih input high voltage cmos levels, 70% of v dd 0.7v dd ?v dd v v il input low voltage cmos levels, 30% of v dd ??0.3v dd v i ih input high current, pd#/oe and sson# pins v in = v dd ??10 a i il input low current, pd#/oe and sson# pins v in = v ss ??10 a i oz output leakage current three-state output, pd#/oe = 0 ?10 10 a c xin or c xout [1] programmable capacitance at pin 2 and pin 3 capacitance at minimum setting ? 12 ? pf capacitance at maximum setting ? 60 ? pf c in [1] input capacitance at pin 4 and pin 8 input pins excluding xin and xout ? 5 7 pf i vdd supply current v dd = 3.45v, fin = 30 mhz, refclk = 30 mhz, ssclk = 66 mhz, c load = 15 pf, pd#/oe = sson# = v dd ?2535ma i dds standby current v dd = 3.45v, device powered down with pd# = 0v (driven reference pulled down) ?1530 a notes: 1. guaranteed by characterization, not 100% tested.
cy25100 document #: 38-07499 rev. *c page 5 of 11 ac electrical characteristics [1] parameter description condition min. typ. max. unit dc output duty cycle ssclk, measured at v dd /2 45 50 55 % output duty cycle refclk, measured at v dd /2 duty cycle of clkin = 50% at input bias 40 50 60 % sr1 rising edge slew rate ssclk from 3 to 100 mhz; refclk from 3 to 100 mhz. 20%?80% of v dd 0.7 1.1 3.6 v/ns sr2 falling edge slew rate ssclk from 3 to 100 mhz; refclk from 3 to 100 mhz. 80%?20% of v dd 0.7 1.1 3.6 v/ns sr3 rising edge slew rate ssclk from 100 to 200 mhz; refclk from 100 to 166 mhz 20%?80% of v dd 1.2 1.6 4.0 v/ns sr4 falling edge slew rate ssclk from 100 to 200 mhz; refclk from 100 to 166 mhz 80%?20% of v dd 1.2 1.6 4.0 v/ns t ccj1 [2] cycle-to-cycle jitter ssclk (pin 7) clkin = ssclk = 166 mhz, 2% spread, refclk off ? 90 120 ps clkin = ssclk = 66 mhz, 2% spread, refclk off ? 100 130 ps clkin = ssclk = 33 mhz, 2% spread, refclk off ? 130 170 ps t ccj2 [2] cycle-to-cycle jitter ssclk (pin 7) clkin = ssclk = 166 mhz, 2% spread, refclk on ? 100 130 ps clkin = ssclk = 66 mhz, 2% spread, refclk on ? 105 140 ps clkin = ssclk = 33 mhz, 2% spread, refclk on ? 200 260 ps t ccj3 [2] cycle-to-cycle jitter refclk (pin 6) clkin = ssclk = 166 mhz, 2% spread, refclk on ? 80 100 ps clkin = ssclk = 66 mhz, 2% spread refclk on ? 100 130 ps clkin = ssclk = 33 mhz, 2% spread, refclk on ? 135 180 ps t stp power-down time (pin 4 = pd#) time from falling edge on pd# to stopped outputs (asynchronous) ? 150 350 ns t oe1 output disable time (pin 4 = oe) time from falling edge on oe to stopped outputs (asynchronous) ? 150 350 ns t oe2 output enable time (pin 4 = oe) time from rising edge on oe to outputs at a valid fre- quency (asynchronous) ? 150 350 ns t pu1 power-up time, crystal is used time from rising edge on pd# to outputs at valid fre- quency (asynchronous) ?3.5 5 ms t pu2 power-up time, reference clock is used time from rising edge on pd# to outputs at valid fre- quency (asynchronous), reference clock at correct frequency ?2 3ms application circuit [3, 4, 5] 2. jitter is configuration dependent. actual jit ter is dependent on xin jitter and edge rate, number of active outputs, output f requencies, spread percentage, temper- ature, and output load. for more information, refer to the applic ation note, ?jitter in pll based systems: causes, effects, and solutions? available at http://www.cypress.com/clock/appnotes.html, or contac t your local cypress field application engineer. 3. since the load capacitors (c xin and c xout ) are provided by the cy25100, no external capacitors are needed on the xin and xout pins to match the crystal load capacitor (c l ). only a single 0.1- f bypass capacitor is required on the v dd pin. 4. if an external clock is used, apply the clock to xin (pin 3) and leave xout (pin 2) floating (unconnected). 5. if sson# (pin 8) is low (v ss ), the frequency modulation will be on at ssclk pin (pin 7). 0.1uf vdd 1 3 2 4 5 6 7 8 vdd xout xin/clkin pd#/oe vss refclk ssclk sson# power cy25100
cy25100 document #: 38-07499 rev. *c page 6 of 11 switching waveforms duty cycle timing (dc = t 1a /t 1b ) t 1a t 1b output output rise/fall time (ssclk and refclk) output tr v dd 0v tf output rise time (tr) = (0.6 x v dd )/sr1 (or sr3) output fall time (tf) = (0.6 x v dd )/sr2 (or sr4) refer to ac electrical characteristics table for sr (slew rate) values. power-down timing and power-up timing clkout v dd t pu t stp v il v ih power- down 0v (asynchronous ) high impedance output enable/disable timing clkout v dd t oe1 v il v ih output enable 0v (asynchronous ) high impedance t oe2
cy25100 document #: 38-07499 rev. *c page 7 of 11 informational graphs [6] note: 6. the ?informational graphs? are meant to convey the typical per formance levels. no performance sp ecifications is implied or gu aranteed. refer to the tables on pages 4 and 5 for device specifications. spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= -4% 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 fnominal 0 20 40 60 80 100 120 140 160 180 200 time (us) spread spectrum profile: fnom=166mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= -4% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 68.5 68 67.5 67 66.5 66 65.5 65 64.5 6 4 63.5 spread spectrum profile: fnom=66mhz, fmod=30khz, spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 time (us) fnominal 67.5 67 66.5 66 65.5 65 64.5 duty cycle vs. refclk ( cload=15pf) 40 42 44 46 48 50 52 54 56 58 60 0 50 100 150 200 refcl k ( m hz ) duty cycle (%) idd vs. ssclk te m perature=25c, vdd=3.3v, cload=15pf, ss off, re fclk = 30m hz 0 5 10 15 20 25 30 0 50 100 150 200 ssclk (m hz) idd (m a )
cy25100 document #: 38-07499 rev. *c page 8 of 11 informational graphs (continued) [6] measured spread% vs. vdd over tem perature (target spread = 0.5%, fout=100mhz, c load =15pf) 0.40% 0.45% 0.50% 0.55% 0.60% 2.7 3 3.3 3.6 3.9 vdd (v) spread% -40c 25c 85c measured spread% vs. vdd over temperature (target spread = 5.0%, fout=100mhz, c load =15pf) 4.00% 4.50% 5.00% 5.50% 6.00% 2.7 3 3.3 3.6 3.9 vdd (v) spread% -40c 25c 85c ssclk attenuation vs. vdd over temperature (measured at 7th harmonic w ith fnom=100mhz and spread=0.5%, c load =15pf) -10 -8 -6 -4 -2 0 2.7 3 3.3 3.6 3.9 vdd (v) attenuation (db) -40c 25c 85c ssclk attenuation vs. vdd over tem perature (measured at 7th harmonic w ith fnom=100mhz and spread=5.0%, c load =15pf) -20 -18 -16 -14 -12 -10 2.7 3 3.3 3.6 3.9 vdd (v) attenuation (db) -40c 25c 85c ssclk emi attenuation vs. spread% (measured at 7th harmonic temp=25c, vdd=3.3v, ssclk=100mhz, measured on cypress characterization board w ith cload=15pf) -16 -14 -12 -10 -8 -6 -4 -2 0 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% 4.0% 4.5% 5.0% spre ad % attenuation (db) max cycle-cycle jitter on ssclk vs. temperature (ssclk=100mhz, vdd=3.3v, cload=15pf, +/- 2%spread, refclk off) 0 25 50 75 100 125 150 175 200 -40 -20 0 20 40 60 80 100 temperature (deg c) jitter (ps)
cy25100 document #: 38-07499 rev. *c page 9 of 11 ordering information part number [7] package description product flow cy25100scf 8-pin small outline integrated circuit (soic) commercial, 0 to 70c cy25100sif 8-pin small outline integrated circuit (soic) industrial, ?40 to 85c cy25100zcf 8-pin thin shrunk small outline package (tssop) commercial, 0 to 70c cy25100zif 8-pin thin shrunk small outline package (tssop) industrial, ?40 to 85c cy25100sc-xxxw 8-pin small out line integrated circuit (soic) commercial, 0 to 70c cy25100sc-xxxwt 8-pin small outline integr ated circuit (soic) ? tape and reel commercial, 0 to 70c cy25100si-xxxw 8-pin small outline integrat ed circuit (soic) industrial, ?40 to 85c cy25100si-xxxwt 8-pin small outline integrated circu it (soic)?tape and reel industrial, ?40 to 85c cy25100zc-xxxw 8-pin thin shrunk small outline package (tssop) commercial, 0 to 70c CY25100ZC-XXXWT 8-pin thin shrunk small outline package (tssop)?tape and reel commercial, 0 to 70c cy25100zi-xxxw 8-pin thin shrunk small outline package (tsso p) industrial, ?40 to 85c cy25100zi-xxxwt 8-pin thin shrunk small outline pa ckage (tssop)?tape and reel industrial, ?40 to 85c cy3672 ftg development kit n/a cy3672-prg ftg programmer n/a cy3690 cy25100zcf socket adapter (tssop) n/a cy3691 cy25100scf socket adapter (soic) n/a package diagrams note: 7. ?xxx? denotes the assigned product dash number. ?w? denotes the different programmed frequency and/or spread % options. seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 8-lead (150-mil) soic s8 51-85066-*c
cy25100 document #: 38-07499 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cyberclocks is a trademark of cypress se miconductor. all product and company nam es mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) 8 pin 1 id seating plane 1 bsc. bsc 0-8 plane gauge 2.90[0.114] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 3.10[0.122] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] 8-lead thin shrunk small outline package (4.40 mm body) z8 51-85093-*a
cy25100 document #: 38-07499 rev. *c page 11 of 11 document history page document title: cy25100 field-and factory-programmable spread spectrum clock generator for emi reduction document number: 38-07499 rev. ecn no. issue date orig. of change description of change ** 126578 06/27/03 ckn new data sheet *a 128753 08/29/03 ijatmp changes to reflect field programmability *b 130342 12/02/03 rgl changes to application circuit diagram and correction to the package de- scription listed under the ordering information table for cy3690 and cy3691. *c 204121 see ecn rgl add industrial temperature range corrected the ordering information to match the devmaster

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